Conventional content addressable memories (i.e., CAMs) compare an input data word with all of the words stored in the CAM. The comparison of the stored words to the input data word (i.e., comparison data word) is done either simultaneously or over a few clock cycles. If any words stored in the CAM match the comparison data word, the CAM presents an output signal (or signals) representing a hit and/or an encoded address of the highest priority matching stored word. Because of how much computation is done in parallel to find the matching words, CAM memories usually have high peak currents and high average power consumptions.
It would be desirable to implement a content addressable memory that provides data clustering block architecture.